1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and particularly to a method of manufacturing a semiconductor device having a contact plug.
2. Related Art
In a semiconductor device, a semiconductor silicon substrate and an upper wiring layer are generally connected by use of a contact plug.
Here, a conventional method of manufacturing a semiconductor device is described with reference to FIGS. 1A through 1E.
As shown in FIG. 1A, an interlayer insulating film 2 made of SiO2 or the like is formed on a semiconductor substrate 1.
Then, a photoresist layer (not shown) is formed at a given position on the aforementioned interlayer insulating film 2, and this photoresist layer is used as a mask in a well-known dry etching process to form a contact hole 3 shown in FIG. 1B.
Next, as shown in FIG. 1C, a sputtering process is performed to form a titanium layer 4 on the surface of the contact hole 3. Then, annealing treatment is performed in an atmosphere of N2 gas thereby to make the titanium layer 4 become a barrier layer 6 of TiN as illustrated in FIG. 1D. At this point, a metal silicide layer 5 of TiSi2 is formed on the semiconductor silicon substrate 1 under the bottom of the contact hole 3.
Then, provided on the aforementioned contact hole 3 is a conducting layer comprised of tungsten, polysilicon containing impurities or the like to form a contact plug 7 as shown in FIG. 1E.
The resistance of the thus formed contact plug is preferably lower so as to reduce power consumption of the semiconductor device. For the purpose of reducing the resistance of the contact plug and the like, there is known a method of forming a TiSi2layer at the bottom of the aforementioned contact hole.
Meanwhile, there is also known a method of manufacturing an insulated gate field effect transistor, as shown in FIGS. 2A and 2B, by implanting the whole surface of the N-type diffusion layer of the semiconductor silicon substrate with indium ions.
This method is explained below:
First, as shown in FIG. 2A, a device separation insulating region 13 and an insulating film 14 are formed on the semiconductor silicon substrate. Then, phosphorus ions and boron ions are implanted into the semiconductor silicon substrate and thereby, a P-type well 8 and an N-type well 9 are formed in the semiconductor silicon substrate.
This is followed by selectively implanting boron ions into the P-type well 8 and phosphorus ions into the N-type well 9. Then, a P-type high-concentration well layer 10 and an N-type high-concentration well layer 11 are formed on the P-type well 8 and the N-type well 9, respectively.
After that, indium ions are implanted into the whole surface of the P-type well 8 and the N-type well 9 and thereby, an indium-containing layer 12 is formed on the semiconductor silicon substrate.
Further, as shown in FIG. 2B, arsenic ions are selectively implanted into the P-type high-concentration well layer 10 with a gate electrode structure 20, which is provided on the semiconductor silicon substrate, used as an implantation blocking mask, and thereby high-concentration N-type diffusion layers 15 and 16 are formed.
Likewise, BF2 ions are selectively implanted into the N-type high-concentration well layer 11 and thereby high-concentration P-type diffusion layers 17 and 18 are formed.
Here, the high-concentration N-type diffusion layers 15 and 16 and the high-concentration P-type diffusion layers 17 and 18 correspond to a source/drain structure of the insulated gate field effect transistor.
The just-described method of manufacturing a semiconductor device having an indium-containing layer, is proposed in Japanese Patent Application Publication No. 2002-368212.